1. Field of the Invention
This invention relates generally to memory devices and more particularly to NOR-type mask ROM (Read Only Memory) devices.
2. Description of the Related Art
To meet demands for ROM devices having higher integration levels, lower cost, and higher speed, designers of mask ROMs have migrated from conventional NOR-type cells to conventional NAND-type cell designs, and back to NOR-type cell designs having a flat structure. A conventional NOR-type cell can be easily realized to achieve high speeds through the use of high cell currents. However, a disadvantage of this approach is that the area of each cell is enlarged, thus increasing the overall size of the semiconductor memory device. Since the area of a NAND-type cell is small, and since each cell has a low cell current, NAND-type cells have been used to achieve high integration levels at the expense of lower speeds.
Recently, NOR-type flat cells ( which do not include field oxidation films for separating units within a cell array) have been developed because they retain the speed advantages of conventional NOR-type cells but can also be miniaturized like the NAND-type cells. NOR-type flat cells have high cell current values, and since NOR-type cells have superior cell uniformity, multi-bit or multi-state concepts can be utilized to store several bits of information within one cell.
The operation of several prior art NOR-type memory cells will be described with reference to FIGS. 1-4 in which components performing similar functions are identified by similar reference designators. Selection transistors designated with the symbol "S" are maintained in the on-state when the power source voltage VCC is applied thereto. "S" election transistor which do not having the reference symbol "S" are maintained in the off-state even when the power source voltage VCC is applied thereto. The reference symbol FOX1 represents a field oxide region for separating units between two bit lines. Also, the regions drawn with diagonal slanting lines represent buried diffusion layers.
The structure of the portion of the memory cell array which includes word lines WL1-WLn is generally the same for the arrays shown in FIGS. 1-4. The differences between the arrays shown in FIGS. 1-4 are generally in the manner in which the current drive ability of the selection transistors are improved in the discharge path from a bit line to a ground line. The cell selection transistors are fabricated using the same design rule as the memory cell array. Thus, when the design rule decreases, the number of the selection transistor connected in series with the path from the bit lines to ground lines should be decreased, the channel width should be increased to improve the cell driving ability, or the resistance of the buried impurity regions should be reduced.
Referring to FIG. 1, main bit line ML2 is located between ground lines ML1 and ML3, and main bit line ML4 is located between ground lines ML3 and ML5. All of the lines are made of metal. Buried N.sup.+ impurity diffusion layers form sub-bit lines SBL1-SBL9 which are arranged on a substrate in parallel with the bit and ground lines. Odd numbered ones of the sub-bit lines SBL1-SBL1, such as SBL1, SBL3, SBL5, SBL7 and SBL9, are electrically connected with the main bit lines ML2 and ML4 and the ground lines ML1, ML3 and ML5 through bit line contacts and main bank selection transistors, respectively. Bank selection transistors S are formed at the cross-point in which are bank selection lines BS1 and BS4 intersect with the main bit lines ML1-ML5.
Odd numbered ones SBLi (i=1,3,5 . . . ) of sub-bit lines SBL1-SBL9 are selectively connected with even numbered ones through sub-bank selection transistors, respectively, wherein the sub-bank transistors S are formed at the cross-point in which the sub-bank selection lines BS2 and BS3 intersect with the main bit lines ML1-ML5. The sub-bit lines SBLi (i=1,2,3 . . . ) formed by the buried N.sup.+ impurity diffusion layers are used as drain and source therein. Thus, when one of the memory cells is selected, the main bank selection transistors S located at the top and bottom are set to the logic "high" level so that the bank selection line BS1 and BS4 and the sub-bank selection line BS2 and BS3 can be activated therein. Also, when the odd numbered bank selection transistor SBLi is at a logic "high" level, and the even numbered bank selection transistor SBLk is at a logic "low level, the sub-bit lines are electrically connected with each other so that the sub-bit lines positioned adjacent each other are used for as source and drain, and the row of the memory cell array having the channel of a memory cell transistor between the sub-bit lines is selected. Thus, for the above operation, the ground lines NILL, ML3 and ML5 are electrically connected with the sub-bank selection line BS2 and BS3.
Then, when a word line WLi is selected and placed in a logic "high" level, current flows to the ground lines from the main bit lines in accordance with the value of the threshold voltage Vth of the memory cell selected. For example, if the voltage applied to the selected word line WLi is 3 V, the threshold voltage Vth of an on-cell is set to about 0.51-1.5 V, while the threshold voltage Vth of an off-cell should be higher than 3 V . Also, when a nearby column is selected, the biasing voltage applied to the sub-bank selection transistor as stated in the above example should the opposite of that described above.
The cell operation of the device shown in FIG. 2 is similar to that shown in FIG. 1, but there are minor differences in the construction of the main bank selection transistor. First, the main bank selection transistor in FIG. 1 is formed as a conventional transistor where the drain/source is formed by self-alignment ion injection after the formation of a gate rather than as a buried transistor as in FIG. 2. Second, bit lines BL1 and BL2 are separated by field oxide. In addition, the drain is connected to the main bit line BLi through a contact, and the source is formed from a conventional N.sup.+ diffusion layer electrically connected to the buried diffusion layer SB1 to SB4 of the memory cell.
In general, the resistance of the buried diffusion layer of the memory cell should correspond to a logic "low" if possible. However, it is very difficult to maintain the density of dose at a given density because of the reduction the channel length and punch through margin by a subsequent heat budget. Hence, the current driving ability of the buried transistors, i.e., the bank selection transistors, deteriorates. Further, because over-etching can occur when the contact hole is formed, a shallow junction in accordance with low density doping of the source/drain causes deterioration of the junction breakdown voltage. Therefore, the main bank selection transistors of the prior art array of FIG. 1 has a superior construction comparing with that of FIG. 2. Furthermore, reduction of doping by the reduction of the design rule at the buried diffusion layer can result in improved performance from that described above.
Referring to FIG. 3, a current path from the bit line to the ground line, which has a .orgate. type or a .andgate. type (U-type or inverted U-type), is formed by the bank selection transistors located at the top and bottom and makes a transition from the logic low level to the logic high level or from the logic high level to the logic low level. Further, in comparison with the arrays shown in FIGS. 1 and 2, the number of transistor in the current path is reduced, and thus, the cell current is superior. However, a problem with the design shown in FIG. 3 is that the channel width of the bank selection transistors is restricted and the length of the channel is non-uniform. Also, since the main bit lines are connected with one of the sub-bit lines, bit line charging must occur, and this reduces the speed of the device due to the high junction capacitance.
Referring to FIG. 4, the sensing structure of a source line is formed from the buried diffusion layers (drawn with slanted lines) which are connected with the ground lines MG1 to MG5 wherein the ground lines MG1 to MG5 are arranged between sub-bit lines SB1 to SB4 connected to one main bit line MB1.
Accordingly, a need remains for a mask ROM which overcomes the limitations of the prior art.